1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) device. In particular, the present invention relates to a semiconductor IC device including a stacked dynamic random access memory (stacked DRAM) or a chip on chip DRAM (COC DRAM).
2. Description of the Related Art
FIG. 1 shows an example of a memory system which is presently studied by Joint Electron Device Engineering Council (JEDEC).
The memory system shown in FIG. 1 includes a chip set 4 mounted on a motherboard (not shown) and a plurality of (two of them are shown here) dual inline memory modules (DIMMs) 1a and 1b for transmitting/receiving signals to/from the chip set 4. A buffer 2a or 2b and a plurality of (8 in this case) DRAM chips 3a or 3b are mounted on each of the DIMMs 1a and 1b. 
The chip set 4 is connected to the buffer 2a of the DIMM 1a and the buffers 2a and 2b of the adjoining DIMMs 1a and 1b are connected to each other so that signals are transmitted/received therebetween by point-to-point. The data rate of the signals is estimated to be about 6.4 to 9.6 Gbps. The signals transmitted/received between the chip set 4 and each of the DIMMs 1a and 1b include a DQ (data) signal and a CA (command address) signal. These signals are transmitted as differential transmission signals. About 150 to 200 signal lines are required for transmitting these signals.
On each of the DIMMs 1a and 1b, the buffer 2 and each DRAM chip 3 are connected by using different methods depending on the types of signals. Specifically, point-to-point connection is used for DQ signals (DQ signal and DQS (strobe) signal). The data rate thereof is estimated to be about 1.6 Gbps. On the other hand, fly-by connection is used for a CA signal and a CLK (clock) signal. In the fly-by connection, a DRAM is placed on a main bus disposed in a module substrate such that the DRAM is connected to the main bus. The number of signal lines led from the buffer 2 is about 200 to 250, including those for differential transmission signals and single-end transmission signals.
The size of the package of the buffer 2 is set to about 21 mm×21 mm to 25 mm×25 mm by considering space for signal balls, VDD balls, GND balls, and no connection, if a ball pitch is 0.8 mm.
Although not shown in FIG. 1, a terminating resistor is provided in a receiving side in point-to-point connection. In fly-by connection, a terminating resistor is provided at a farthest end.
On the other hand, techniques of stacking a plurality of IC chips or large-scale integration (LSI) chips for a purpose of high integration of an IC have been suggested (for example, see Japanese Laid-Open Patent Publication No. 6-291250 (Document 1); U.S. Pat. No. 6,133,640 (Document 2); PCT Japanese Laid-Open Patent Publication No. 9-504654 (Document 3); and the Research Achievement of 2002 by Association of Super-Advanced Electronics Technologies (ASET) (Document 4)).
Document 1 describes a technique of connecting pads for signals of same attribute, such as address signals, by through electrodes. Document 2 describes a technique of stacking a memory-array circuit and a controller circuit. Document 3 describes a technique of stacking a memory chip and an interface LSI. Further, Document 4 describes a technique of forming a transmission line by using a Si interposer.
In the known memory system shown in FIG. 1, the distance between each of the DRAM chips and the buffer 2 in each DIMM is different one from another. Therefore, in this memory system, the buffer must operate according to the farthest DRAM chip, so that it is difficult to increase the operation speed. This problem can be solved to some extent by allowing the buffer to perform synchronizing processing or the like. In that case, however, another problem will arise, that is, the performance of the entire system is degraded and the cost increases.
Also, in the known memory system, the topology of a CLK signal or the like is different from the topology of DQ signals in each DIMM, and thus the difference in arrival time (propagation time) between a CLK signal and a DQS signal is caused in each DRAM chip. The difference must not exceed 15% of one clock cycle in view of the system design, and this cannot be realized if a clock frequency increases.
Further, in the known memory system, a terminating resistor must be provided in every transmission line, so that a large amount of electric power is consumed by the terminating resistors disadvantageously.
Still further, in the known memory system, a single-chip DRAM or a stacked (2-chip) DRAM is used as each DRAM. With this configuration, the occupied area increases as the memory capacity increases.
The above-mentioned Documents 1 to 4 do not at all disclose the entire configuration of the memory system, in particular, the configuration of the interposer, a method for placing through electrodes in a stacked DRAM, or a method for providing a terminating resistor.
Further, in the technique described in Document 4, the thickness of the insulating layer is no less than 10 μm (10 times thicker than an insulating layer which is usually used in LSI). Such a thick insulating layer is difficult to fabricate in an ordinary LSI manufacturing process. In addition, DC resistance Rdc of a transmission line shown in Document 4, having a width of 12.5 μm, a thickness of 1 μm, and a length of 10 mm, is Rdc=( 1/58e6)×(10e−3)/((1e−6)×(12.5e−6))=14Ω. This value is a little too large for a transmission line using a terminating resistor of about 50Ω.